The reliability of circuits has become an increasing concern with technology scaling due to the rapid advances in technology, where devices are being developed using new materials and processes. Time to market concerns make it difficult to fully understand the lifetime of circuits developed using these new materials and processes. As a result, electronic devices are increasingly vulnerable to reliability problems, meaning that components fail sooner than expected. These reliability problems are exacerbated by several factors, including technology scaling, higher operating temperatures, smaller device dimensions, and more powerful electric fields. In some cases, system failure rates in the field have increased by 365% when scaling from 180 nm to 65 nm, and the field failure rate continues to increase.
It is not uncommon for development of each new chip product to cost tens or hundreds of millions of dollars, including tens of millions of dollars for new designs. Related art approaches for determining reliability check if a circuit has adequate lifetime by operating samples of circuits at high voltage and high temperature to accelerate failure, called high-temperature operating life (HTOL) tests. Models are used to relate the failure rate of HTOL tests to the failure rate at use conditions. Correcting defects found during HTOL tests is potentially very expensive, costing millions of dollars to fix any failing design. Building a new mask set for a circuit, for example, costs millions of dollars for advanced technology nodes with design changes creating additional mask costs. Further, the time-to-market is increased when too many chips fail the HTOL test because of design release delays, causing millions of dollars in potential revenue losses.
FIG. 1 illustrates the design process in the related art. As can be seen, the design process includes developing 105 device technology and/or models. The device technology may include a manufacturing process of a completed design. The device models may include models of various hardware components implemented using the technology. In some cases, the device technology and models may be predefined and not readily adjustable. Next, the design process includes designing 110 a circuit based on the device technology and models. Once the circuit is designed 110, samples of the circuit are manufactured 115. After manufacturing 115, functional testing is performed 120, and reliability testing is performed 125. If the samples pass both tests 120 and 125, the design is produced 130 for delivery and distribution. If the device fails either the functional or reliability testing 120 and 125, the failure is analyzed 135 to pinpoint the fault. Then the circuit must be redesigned 110, remanufactured 115, and retested 120 and 125. In some cases, the device technology and/or models must be redeveloped 105 before redesigning 110 the circuit. In some cases, the reliability testing 125 may take several months or more. In the related art, a manufactured design fails the reliability testing up to 5% of the time. The redesign costs from a design failing the reliability testing 125 can be significant, and the delay to market may cost millions more.
In the related art, reliability models for circuit simulation enable simulation of transistors by incorporating certain wearout features in device modules. The related art simulation capacity is limited to estimating wearout due to bias temperature instability (BTI) and hot carrier injection (HCI). However, such related art estimation fails to consider reliability of memory, such as cache memory, associated with different configurations (e.g., associativity, cache line size, cache size, and replacement algorithm used), the effect of error correcting codes (ECCs), real temperature and ohmic potential drop (IR drop) profiles of a microprocessor, and the combined effect of BTI and HCI.
In addition, the related systems fail to consider soft-breakdown due to gate oxide breakdown (GTDDB), backend dielectric breakdown (BTDDB), and middle-of-line time-dependent dielectric breakdown (MTDDB), and hard breakdown. In addition, the related art systems enable degradation estimation of small circuit blocks, but do not incorporate these models into cell libraries. Thus, related art systems are not able to accurately evaluate the impact of degradation on system performance or estimate system lifetime.
Accordingly, there is a need for accurate simulation of expected lifetimes of memory and logic, as well as an entire circuit.